Karl Guttag on Technology

Karl Guttag has over 34 years of experience in integrated circuit architecture related to Graphics and Image Processors Digital Signal Processing (DSP), and memory architecture.  For the last 12 years he has worked on integrated circuit backplanes for Liquid Crystal on Silicon (LCOS) displays. Over the last 34 years he has identified new market opportunities and integrated circuit architectures to serve those markets.

He is named inventor on over 142 issued U.S. Patents including key patents related graphics and imaging processors, graphics interface circuits, microprocessors, signal processing (DSP), Synchronous DRAMs, and Video Rams.  Billions of dollars of yearly revenue have been attributed to products using these inventions.  Mr. Guttag is the youngest person elected to The Fellow of Texas Instruments; he is a named inventor or co-inventor on over 142 US Patents.

Expertise

• Microdisplays particularly Liquid Crystal Display (LCD) on Silicon (LCOS)
• Pico projector technology and applications
• Digital Signal Processors (DSP)
• Multimedia Processors and Multimedia Instruction Sets (SIMD Instructions)
• Semiconductor Memory: SRAM, DRAM & VRAM, Video RAM, Graphics RAM, and Smart Memory architectures
• Microprocessor Design Architecture and logic
• Single Instruction, Multiple Data Stream (SIMD) processors
• Graphics processors and graphics accelerators

Work Summary

Date:                  2004-12 to 2011-12

Organization:   Syndiant, Inc., Richardson, TX

Title:                   Founder and CTO

Summary:          Syndiant is working on Liquid Crystal on Silicon (LCOS) display devices for pico projector applications and were based on Karl Guttag’s inventions.  Syndiant has the leadership position in high resolution LCOS microdisplay for small (pico) projectors.  The devices have been designed into product marketed by 3M, Philips, and AAXA,  among others.  Syndiant’s devices and technology are being considered for integration into cell phones by a number of major companies.

Dates:               2001-07 to 2010-12

Organization:  Kagutech, Ltd.

Title:                  President

Summary:         For this intellectual property company, Mr. Guttag has invented and has issued Patents on new all digital architectures for Microdisplay Backplanes.  The technology he invented at Kagutech by Karl Guttag was exclusively licensed to Syndiant.

Dates:                1998-05 to 2001-06

Organization:   Silicon Display Incorporated

Title:                  CTO

Summary:         A startup company working on Liquid Crystal on Silicon.  During that time Mr. Guttag was responsible for the architecture of a digital LCOS display device and the FPGA that interfaced to the display device as well as developing LCOS drive algorithms.

Dates:               1977-07 to 1998-05

Organization:   Texas Instruments (TI)

Title:                  TI Fellow

Summary:         Most of his 20 years at TI was involved with the integrated circuits related to storing and manipulating graphics, imaging, and video data.  He was the lead integrated circuit architect of some of TI’s most advanced integrated circuits.

While at TI, he was the technical leader on a number of imaging and graphics related programs.  Mr. Guttag was the chief architect of the TMS320C8x (MVP) family (1990-1996) of image processors (which have been often cited in patent/legal procedures against Microunity patents) and the TMS340 family (1984-1989) of programmable graphics processors.

The need for better memory interfaces for graphics and imaging architectures led to his driving the definition of the TMS4161, the first Video DRAM (VRAM) and then he contributed to subsequent higher capacity VRAMs.  These devices reached billions of dollars in world wide revenue before being largely replaced by the Synchronous DRAM and Graphics DRAMs which Karl Guttag helped initiate and architected as a replacement for the Video RAM.  He is a named inventor on key patents related to both the VRAM and SDRAM.

He led the definition of highly integrated Video Interface Palettes at TI (1984-1989).  This development led to a significant product line in the Mixed Signal Product group within TI.   Earlier, Karl Guttag’s work on graphics architectures in 1984 resulted in meetings with newly found Brooktree Inc. which led to their business in color palettes.

He headed the logic and design architecture of the TMS 9995 (1979) and TMS 99000 (1980-1981) 16-bit microprocessors.  Both architectures went to production with only slight modifications to first silicon.  His work on these architectures at a time when TI had had a series of problems building previous processors plus his work on the VRAM, led to him being selected as the youngest Senior Member of Technical Staff (SMTS) at TI in 1982.

In 1977 and 1978, he was one of the 6 original engineers on the TMS9918 “Sprite Chip” family (1977-1979) that was used in Colecovision, the Japanese MSX home computer, and TI’s 99/4 home computer.  This sprite architecture was later cloned and used by Nintendo in their game systems.  He directly worked on the Sprite architecture, DRAM interface definition, and logic verification of the TMS 9918 family (which included the 9918, 9918A, 9928, 9118, and 9128).

Litigation Support

Type of Matter:	Patent infringement litigation
Law Firm:	Withheld
Case Name:	Withheld
Services Provided:	Technical consultant
Disposition:	On going
Date:	2010-09 -
Type of Matter:	Patent infringement litigation
Law Firm:	Finnegan, Henderson, Farabow, Garrett and Dunner L.L.P.
Case Name:	Microunity v. Sony Entertainment
Services Provided:	Technical consulting
Disposition:	Settled before trial
Date:	2007-09 through 2007-11
Type of Matter:	Patent infringement litigation
Law Firm:	Latham & Watkins LLP
Case Name:	St MicroElectronics v. Broadcomm
Services Provided:	Technical consulting
Disposition:	Settled before trial
Date:	2003-05 through 2004-03
Type of Matter:	Patent infringement litigation
Law Firm:	Latham & Watkins LLP
Case Name:	St MicroElectronics v. Broadcomm
Services Provided:	Technical consulting
Disposition:	Settled before trial
Date:	2003-05 through 2004-03
Type of Matter:	Patent infringement litigation
Law Firm:	Munger, Tolles & Olson LLP
Case Name:	Rambus v. N/A
Services Provided:	Technical consulting
Disposition:	Settled before trial
Date:	2002-07 to 2002-10

Education

BSEE from Bradley University in 1976

MSEE from the University of Michigan 1977

Recognition

He was the youngest person elected to Senior Member of Technical staff after only 4.5 years at TI, and was the youngest person elected to TI Fellow at Texas Instruments, receiving this honor after less than 11 years after joining TI.  He was awarded the “Technical Achievement” award by the NCGA in 1988 for his work on the Video RAM.  At SID 2011 he won a Distinguished Paper Award for his paper on “Laser+LCOS Technology Revolution.”

Karl Guttag has been an invited speaker and has published numerous papers at many graphics, imaging, and integrated circuit conferences.   He has been regularly quoted in most of the major electronics and graphics magazines.

Patents

To date, 142 U.S. patents have been issued with Karl Guttag as an inventor.  A number of the patents have been considered key patents in Texas Instruments’ patent portfolio and have resulted in significant licensing revenue to TI.  Most of these patents relate to digital signal processor architecture, graphics and imaging architectures, new DRAM architectures, and video.

Patent	Title
8035627	Bit serial control of light modulating elements
8004505	Variable storage of bits on a backplane
7924274	Masked write on an array of drive bits
7667678	Recursive feedback control of light modulating elements
7389317	Long instruction word controlling plural independent processor operations
7071908	Digital backplane
7039795	System and method for using a two-stage multiplexing architecture for performing combinations of passing, rearranging, and duplicating operations on data
6948050	Single integrated circuit embodying a dual heterogenous processors with separate instruction handling hardware
6829696	Data processing system with register store/load utilizing data packing/unpacking
6803885	Method and system for displaying information using a transportable display chip
6754809	Data processing apparatus with indirect register file access
6711602	Data processor with flexible multiply unit
6370558	Long instruction word controlling plural independent processor operations
6314047	Low cost alternative to large dual port RAM
6260088	Single integrated circuit embodying a risc processor and a digital signal processor
6240437	Long instruction word controlling plural independent processor operations
6232955	Palette devices, systems and methods for true color mode
6219695	Circuits, systems, and methods for communicating computer video output to a remote location
6219688	Method, apparatus and system for sum of plural absolute differences
6219627	Architecture of a chip having multiple processors and multiple memories
6173394	Instruction having bit field designating status bits protected from modification corresponding to arithmetic logic unit result
6116768	Three input arithmetic logic unit with barrel rotator
6098163	Three input arithmetic logic unit with shifter
6088280	High-speed memory arranged for operating synchronously with a microprocessor
6070003	System and method of memory access in apparatus having plural processors and plural memories
6058473	Memory store from a register pair conditional upon a selected status bit
6032170	Long instruction word controlling plural independent processor operations
6016538	Method, apparatus and system forming the sum of data in plural equal sections of a single data word
5995748	Three input arithmetic logic unit with shifter and/or mask generator
5995747	Three input arithmetic logic unit capable of performing all possible three operand boolean operations with shifter and/or mask generator
5982694	High speed memory arranged for operating synchronously with a microprocessor
5974539	Three input arithmetic logic unit with shifter and mask generator
5961635	Three input arithmetic logic unit with barrel rotator and mask generator
5960193	Apparatus and system for sum of plural absolute differences
5956744	Memory configuration cache with multilevel hierarchy least recently used cache entry replacement
5923340	Process of processing graphics data
5912854	Data processing system arranged for operating synchronously with a high speed memory
5808958	Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock
5805913	Arithmetic logic unit with conditional register source selection
5768609	Reduced area of crossbar and method of operation
5761726	Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor
5742538	Long instruction word controlling plural independent processor operations
5734880	Hardware branching employing loop control registers loaded according to status of sections of an arithmetic logic unit divided into a plurality of sections
5727225	Method, apparatus and system forming the sum of data in plural equal sections of a single data word
5724599	Message passing and blast interrupt from processor
5712999	Address generator employing selective merge of two independent addresses
5701507	Architecture of a chip having multiple processors and multiple memories
5696959	Memory store from a selected one of a register pair conditional upon the state of a selected status bit
5696954	Three input arithmetic logic unit with shifting means at one input forming a sum/difference of two inputs logically anded with a third input logically ored with the sum/difference logically anded with an inverse of the third input
5696913	Unique processor identifier in a multi-processing system having plural memories with a unified address space corresponding to each processor
5694348	Method apparatus and system for correlation
5673407	Data processor having capability to perform both floating point operations and memory access in response to a single instruction
5651127	Guided transfers with variable stepping
5644524	Iterative division apparatus, system and method employing left most one’s detection and left most one’s detection with exclusive or
5640578	Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section
5634065	Three input arithmetic logic unit with controllable shifter and mask generator
5613146	Reconfigurable SIMD/MIMD processor using switch matrix to allow access to a parameter memory by any of the plurality of processors
5606520	Address generator with controllable modulo power of two addressing capability
5600847	Three input arithmetic logic unit with mask generator
5596767	Programmable data processing system and apparatus for executing both general purpose instructions and special purpose graphic instructions
5596763	Three input arithmetic logic unit forming mixed arithmetic and boolean combinations
5596519	Iterative division apparatus, system and method employing left most one’s detection and left most one’s detection with exclusive OR
5592405	Multiple operations employing divided arithmetic logic unit and multiple flags register
5590350	Three input arithmetic logic unit with mask generator
5587954	Random access memory arranged for operating synchronously with a microprocessor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock
5560030	Transfer processor with transparency
5537563	Devices, systems and methods for accessing data using a gun preferred data organization
5524265	Architecture of transfer processor
5522083	Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors
5522082	Graphics display processor, a graphics display system and a method of processing graphics data with control signals connected to a central processing unit and graphics circuits
5517609	Graphics display system using tiles of data
5512896	Huffman encoding method, circuit and system employing most significant bit change for size detection
5509129	Long instruction word controlling plural independent processor operations
5493646	Pixel block transfer with transparency
5493524	Three input arithmetic logic unit employing carry propagate logic
5487146	Plural memory access address generation employing guide table entries forming linked list
5485411	Three input arithmetic logic unit forming the sum of a first input anded with a first boolean combination of a second input and a third input plus a second boolean combination of the second and third inputs
5479166	Huffman decoding method, circuit and system employing conditional subtraction for conversion of negative numbers
5471592	Multi-processor with crossbar link of processors and memories and method of operation
5465224	Three input arithmetic logic unit forming the sum of a first Boolean combination of first, second and third inputs plus a second Boolean combination of first, second and third inputs
5437011	Graphics computer system, a graphics system arrangement, a display system, a graphics processor and a method of processing graphic data
5434969	Video display system using memory with a register arranged to present an entire pixel at once to the display
5420809	Method of operating a data processing apparatus to compute correlation
RE34881	Graphics data processing apparatus having image operations with transparent color having selectable number of bits
5398316	Devices, systems and methods for accessing data using a pixel preferred data organization
5390149	System including a data processor, a synchronous dram, a peripheral device, and a system clock
5375198	Process for performing a windowing operation in an array move, a graphics computer system, a display system, a graphic processor and a graphics display system
5371896	Multi-processor having control over synchronization of processors in mind mode and method of operation
5371517	Video interface palette, systems and method
5333261	Graphics processing apparatus having instruction which operates separately on X and Y coordinates of pixel location registers
5327159	Packed bus selection of multiple pixel depths in palette devices, systems and methods
5317333	Graphics data processing apparatus with draw and advance operation
5309551	Devices, systems and methods for palette pass-through mode
5294918	Graphics processing apparatus having color expand operation for drawing color graphics from monochrome data
5293468	Controlled delay devices, systems and methods
5287100	Graphics systems, palettes and methods with combined video and shift clock control
5283863	Process for effecting an array move instruction, a graphics computer system, a display system, a graphics processor and graphics display system
5270973	Video random access memory having a split register and a multiplexer
5269001	Video graphics display memory swizzle logic circuit and method
5249266	Data processing apparatus with self-emulation capability
5239654	Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode
5231694	Graphics data processing apparatus having non-linear saturating operations on multibit color data
5226125	Switch matrix having integrated crosspoint logic and method of operation
5212777	Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation
5185859	Graphics processor, a graphics computer system, and a process of masking selected bits
5163024	Video display system using memory with parallel and serial access employing serial shift registers selected by column address
5162784	Graphics data processing apparatus with draw and advance operation
5142621	Graphics processing apparatus having instruction which operates separately on X and Y coordinates of pixel location registers
5140687	Data processing apparatus with self-emulation capability
5095301	Graphics processing apparatus having color expand operation for drawing color graphics from monochrome data
5077678	Graphics data processor with window checking for determining whether a point is within a window
5056041	Data processing apparatus with improved bit masking capability
4933878	Graphics data processing apparatus having non-linear saturating operations on multibit color data
4825390	Color palette having repeat color data
4799053	Color palette having multiplexed color look up table loading
4752893	Graphics data processing apparatus having image operations with transparent color having a selectable number of bits
4747081	Video display system using memory with parallel and serial access employing serial shift registers selected by column address
4720819	Method and apparatus for clearing the memory of a video computer
4718024	Graphics data processing apparatus for graphic image operations upon data of independently selectable pitch
4694391	Compressed control decoder for microprocessor system
4688197	Control of data access to memory for improved video system
4663735	Random/serial access mode selection circuit for a video memory system
4660156	Video system with single memory space for instruction, program data and display data
4656596	Video memory controller
4648077	Video serial accessed memory with midline load
4639890	Video display system using memory with parallel and serial access employing selectable cascaded serial shift registers
4603381	Use of implant process for programming ROM type processor for encryption
4590552	Security bit for designating the security status of information stored in a nonvolatile memory
4566075	Table lookup multiplier employing compressed data read only memory
4544851	Synchronizer circuit with dual input
4532587	Single chip processor connected to an external memory chip
4521853	Secure microprocessor/microcomputer with secured memory
4521852	Data processing device formed on a single semiconductor substrate having secure memory
4469964	Synchronizer circuit
4450519	Psuedo-microprogramming in microprocessor in single-chip microprocessor with alternate IR loading from internal or external program memories
4434462	Off-chip access for psuedo-microprogramming in microprocessor
4422143	Microprocessor ALU with absolute value function
4403284	Microprocessor which detects leading 1 bit of instruction to obtain microcode entry point address
4402044	Microprocessor with strip layout of busses, ALU and registers
4402043	Microprocessor with compressed control ROM
4402042	Microprocessor system with instruction pre-fetch
4243984	Video display processor